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PIC17C4X
DS30412C-page 110
1996 Microchip Technology Inc.
TABLE 15-2:
PIC17CXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
16-bit Opcode
Status
Affected
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
f,d
ADD WREG to f
1
0000 111d
ffff
OV,C,DC,Z
ADDWFC
f,d
ADD WREG and Carry bit to f
1
0001 000d
ffff
OV,C,DC,Z
ANDWF
f,d
AND WREG with f
1
0000 101d
ffff
Z
CLRF
f,s
Clear f, or Clear f and Clear WREG
1
0010 100s
ffff
None
3
COMF
f,d
Complement f
1
0001 001d
ffff
Z
CPFSEQ
f
Compare f with WREG, skip if f = WREG
1 (2)
0011 0001
ffff
None
6,8
CPFSGT
f
Compare f with WREG, skip if f > WREG
1 (2)
0011 0010
ffff
None
2,6,8
CPFSLT
f
Compare f with WREG, skip if f < WREG
1 (2)
0011 0000
ffff
None
2,6,8
DAW
f,s
Decimal Adjust WREG Register
1
0010 111s
ffff
C3
DECF
f,d
Decrement f
1
0000 011d
ffff
OV,C,DC,Z
DECFSZ
f,d
Decrement f, skip if 0
1 (2)
0001 011d
ffff
None
6,8
DCFSNZ
f,d
Decrement f, skip if not 0
1 (2)
0010 011d
ffff
None
6,8
INCF
f,d
Increment f
1
0001 010d
ffff
OV,C,DC,Z
INCFSZ
f,d
Increment f, skip if 0
1 (2)
0001 111d
ffff
None
6,8
INFSNZ
f,d
Increment f, skip if not 0
1 (2)
0010 010d
ffff
None
6,8
IORWF
f,d
Inclusive OR WREG with f
1
0000 100d
ffff
Z
MOVFP
f,p
Move f to p
1
011p pppp
ffff
None
MOVPF
p,f
Move p to f
1
010p pppp
ffff
Z
MOVWF
f
Move WREG to f
1
0000 0001
ffff
None
MULWF
f
Multiply WREG with f
1
0011 0100
ffff
None
9
NEGW
f,s
Negate WREG
1
0010 110s
ffff
OV,C,DC,Z
1,3
NOP
—
No Operation
1
0000 0000
0000
None
RLCF
f,d
Rotate left f through Carry
1
0001 101d
ffff
C
RLNCF
f,d
Rotate left f (no carry)
1
0010 001d
ffff
None
RRCF
f,d
Rotate right f through Carry
1
0001 100d
ffff
C
RRNCF
f,d
Rotate right f (no carry)
1
0010 000d
ffff
None
SETF
f,s
Set f
1
0010 101s
ffff
None
3
SUBWF
f,d
Subtract WREG from f
1
0000 010d
ffff
OV,C,DC,Z
1
SUBWFB
f,d
Subtract WREG from f with Borrow
1
0000 001d
ffff
OV,C,DC,Z
1
SWAPF
f,d
Swap f
1
0001 110d
ffff
None
TABLRD
t,i,f
Table Read
2 (3)
1010 10ti
ffff
None
7
Legend: Refer to Table 15-1 for opcode eld descriptions.
Note 1: 2’s Complement method.
2: Unsigned arithmetic.
3: If s = '1', only the le is affected: If s = '0', both the WREG register and the le are affected; If only the Working
register (WREG) is required to be affected, then f = WREG must be specied.
4: During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkk is loaded into
the LSB of the PC (PCL)
5: Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruc-
tion is terminated by an interrupt event. When writing to external program memory, it is a two-cycle instruc-
tion.
6: Two-cycle instruction when condition is true, else single cycle instruction.
7: Two-cycle instruction except for TABLRD to PCL (program counter low byte) in which case it takes 3 cycles.
8: A “skip” means that instruction fetched during execution of current instruction is not executed, instead an
NOP is executed.
9: These instructions are not available on the PIC17C42.
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